EDN

Design faults leading to clock and data glitches

With the increasing complexity of SoCs, multiple and independent clocks are essential in the design. The design specifications require system level muxing of some of these clocks before they are sent ...
EDN

The history and future of scan design

For more than four decades, scan technology has somehow eluded the radar screen of the IC test industry. As test continues to evolve and make significant newsworthy changes, scan has maintained a ...
Semiconductor Engineering

Power Reduction Through Sequential Optimization

Dealing with power is a multifaceted challenge and is an equal-opportunity problem — everybody can contribute to the solution and at many levels of abstraction. At the architectural or system level, ...
Design-Reuse

Averant Adds RTL and Gate Level Combinational Equivalency Checker

HAYWARD, Calif.--August 01, 2011--Averant Inc., the First In Formalâ„¢ leader in property verification of RTL designs for digital circuits, today announces the release of Solidify 5.4. Some of the ...
Design-Reuse

The history and future of scan design

For more than four decades, scan technology has somehow eluded the radar screen of the IC test industry. As test continues to evolve and make significant newsworthy changes, scan has maintained a ...